Propagation Delay (RC)

Calculate RC time constant and delay to a voltage threshold for rising/falling step responses.

How to Use

  1. Enter R and C (or use presets).
  2. Choose the edge: Rising (0→VDD) or Falling (VDD→0).
  3. Set the threshold as a percent or as a voltage (optional).
  4. Open Show Work to see the exact formula and steps.
RC Step Response
Delay is computed to your selected threshold.
τ
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Threshold
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tpd
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Edge
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Status: —
t → V(t) Vth tₚd Visual is illustrative. Exact delay comes from the formulas in Show Work.
Inputs & Settings
Enter R and C. Choose a threshold. Results update instantly.
Typical: 1kΩ–1MΩ (depends on current + noise tolerance)
Typical: pF–µF (watch leakage and tolerance)
Common: 1.8V, 3.3V, 5V, 12V
Used for both rising and falling delay models.
Optional alternative to %. JS will keep modes separate (no guessing).
Tip: 50% threshold is common for “tPD” in digital timing approximations.
Show Work (step-by-step)
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Work is shown in base units (Ω, F, V, s). Time is scaled for display only.

RC Propagation Delay Formulas

Time constant: τ = R × C

For an ideal step response starting at 0V or VDD:

  • Rising (0 → VDD): V(t) = VDD × (1 − e^(−t/τ))
  • Falling (VDD → 0): V(t) = VDD × e^(−t/τ)
  • Solve for time to threshold VTH:
    • Rising: t = −τ × ln(1 − VTH/VDD)
    • Falling: t = −τ × ln(VTH/VDD)
Where R = ohms, C = farads, τ = seconds, VDD and VTH in volts.

FAQ

Why is 63.2% special?

At t = 1τ, a rising RC reaches about 63.2% of VDD (and a falling RC decays to 36.8% of VDD).

Is this “digital propagation delay” exact?

It’s an ideal RC approximation (good for intuition, filters, debounce, simple edge shaping). Real logic delays include driver resistance, input capacitance, thresholds, and loading.

What threshold should I use?

Many timing approximations use 50%. Some CMOS inputs switch closer to ~30–70% depending on family and conditions.

Tool Info

Last updated:

Updates may include more threshold modes, unit coverage, and edge-case handling.